In one known process for fabricating circuitized structures, such as printed circuit boards, electroless additive plating is employed to plate metal, such as copper, to form circuitization onto the structure's dielectric surfaces. In forming such circuitization for these structures, the structure's surface may be photoimaged dielectric, having through holes photoimaged in the dielectric, and may be blanket-coated with seed. Next, a photoresist may be blanket-coated onto the seed layer and photoimaged in a pattern corresponding to the designed circuitization pattern. The line channels may then be developed away, and the structure immersed in an electroless plating bath so that copper may be additively plated in the channels atop the exposed seed; copper may simultaneously be plated into the through holes. The photoresist may then be stripped, leaving circuitization atop the dielectric. The seed which does not have copper deposited thereon, may then be removed. If desired, the copper may then be further plated.
Conventional seeding and electroless plating circuitization methods often suffer from excessive seed deposition; the presence of excessive seed on a circuit board leads to leakage shorts and poor adhesion of the photoresist onto the seed due to a non-homogeneous surface. Excess seed can also lead to unwanted metal plating in subsequent steps.
Conventional seeding and electroless plating methods can also suffer from non-uniform electroless plating within the circuitization line channels, resulting in unwanted skip plating or defects.
It is, therefore, desirable to provide a method for depositing seed which does not result in excessive seed deposition or non-uniform electroless plating within the circuitization line channels. Circuit boards produced with this method should have lower levels of plating circuit line defects and shorts. This would also reduce the need for excessive inspection and improve outgoing product quality levels.